This invention relates generally to analog-to-digital converters, and, more particularly, to analog-to-digital converters of the successive approximation type. Successive approximation is a common technique employed in analog-to-digital conversion, and consists in making successive comparisons between an unknown analog input signal and a precisely generated internal voltage.
A successive approximation register in the converter is adjusted bit by bit during the conversion, and, after each one-bit trial adjustment, its contents are converted to a corresponding analog signal and compared with the unknown signal to be converted. More specifically, the successive approximation register is first cleared, the first or most significant bit is set to a one, and the corresponding analog value is compared with the analog input signal. If the analog input signal is greater than the analog signal corresponding to this first trial setting of the successive approximation register, the most significant bit is left in the set condition, but if the analog input signal is less than the analog signal corresponding to the register setting, the most significant bit is reset to zero. The process is repeated for the next most significant bit, and so forth until conversion has been effected to a desired resolution. Sequencing control logic, under the control of a clock signal and a start-convert signal, control operations on the successive approximation register.
Successive approximation analog-to-digital converters of the prior art are basically synchronous devices. Their rate of operation is determined by the number of bits of resolution required and by an additional fixed period of time required for housekeeping operations, such as clearing the successive approximation register. Moreover, the start-convert command must be given within some relatively small time frame with respect to the occurrence of a clock signal, and the user of the converter must therefore time the start-convert signals accordingly if they are to be accepted by the analog-to-digital converter.
For example, in a ten-bit converter, the conversion time will probably be ten clock cycles, and the housekeeping time may be an additional clock cycle, making eleven clock cycles in all for a complete conversion. A user of such a converter would typically provide start-convert signals every eleven clock cycles, and would synchronize the start-convert signals to the clock signals using external, user-supplied circuitry. One technique for avoiding this burden on the user is to stop the clock between conversions and to start it only on receipt of the start-convert command. Although this solution is satisfactory in many cases, there may be situations in which one would not wish to stop the clock between conversions. In any event, there is a further difficulty, now to be discussed, related to operation of successive approximation converters in a short-cycling mode, and stopping the clock does not provide any solution in this regard.
Short cycling is a mode of operation of successive approximation converters that is frequently made available to users. The term "short cycling" refers to the premature termination of a conversion in progress in order to produce a conversion result of lower resolution, but in a shorter time, than if the conversion ran to completion using the full resolution capacity of the converter. Short cycling is usually implemented by connecting the successive approximation register outputs to output pins of the converter device, and monitoring the successive approximation register in order to determine when a particular resolution has been obtained. It will be recalled that, at each stage of conversion, a particular bit is set, and then either reset or not, depending upon the result of a comparison made between the analog equivalent of the value in the register and the analog input signal being converted. When the setting of a selected bit is observed, an interrupt signal can be fed back to the bit sequencing logic to stop the conversion prematurely.
One significant difficulty with this technique is that it may be too late to stop the conversion as desired if the inherent delay time in generating the interrupt signal is approximately equal to, or even greater than, a clock cycle time for the device. Another difficulty is that the successive approximation register must be made continuously available for monitoring, in order to generate the interrupt signal, and a separate buffered output register cannot, therefore, be conveniently employed. At high speeds of operation, the successive approximation register will contain the final converted result for only a very short time before it is cleared for the next conversion. For example, the clock cycle times contemplated for devices of the same type as the present invention are in the order of 100 nanoseconds (ns). Ideally, from a user standpoint it would be appropriate to have a buffered output register that would contain the correct converted quantity for a relatively long period, perhaps for a full conversion cycle, but to still retain the ability to provide a short-cycling mode of operation, by means of which higher conversion speeds can be attained at the expense of a lower resolution. It will be appreciated, then, that there is a significant need for an analog-to-digital converter of the successive approximation type which avoids the foregoing disadvantages. The present invention is directed to this end.